1. Technical Field of the Invention
The present disclosure relates generally to semiconductor memories. More particularly, and not by way of any limitation, the present disclosure is directed to a system and method for compiling a memory assembly with redundancy.
2, Description of Related Art
Silicon manufacturing advances today allow true single-chip systems to be fabricated on a single die (i.e., System-On-Chip or SOC integration). However, there exists a “design gap” between today's electronic design automation (EDA) tools and the advances in silicon processes which recognizes that the available silicon real-estate has grown much faster than has designers' productivity, leading to underutilized silicon. Unfortunately, the trends are not encouraging: the “deep submicron” problems of non-convergent timing, complicated timing and extraction requirements, and other complex electrical effects are making silicon implementation harder. This is especially acute when one considers that analog blocks, non-volatile memory, random access memories (RAMs), and other “non-logic” cells are being required. The gap in available silicon capacity versus design productivity means that without some fundamental change in methodology, it will take hundreds of staff years to develop leading-edge integrated circuits (ICs).
Design re-use has emerged as the key methodology solution for successfully addressing this time-to-market problem in semiconductor IC design. In this paradigm, instead of re-designing every part of every IC chip, engineers can re-use existing designs as much as possible and thus minimize the amount of new circuitry that must be created from scratch. It is commonly accepted in the semiconductor industry that one of the most prevalent and promising methods of design re-use is through what are known as Intellectual Property (“IP”) components—pre-implemented, re-usable modules of circuitry that can be quickly inserted and verified to create a single-chip system. Such re-usable IP components are typically provided as megacells, cores, macros, embedded memories through generators or memory compilers, et cetera.
It is well known that memory is a key technology driver for SOC design. Although providing high quality embedded memory IP in SOC applications poses several challenges, the total density of embedded memory has been increasing rapidly. It should be appreciated that without the use of redundancy, the fabrication yields of SOC devices and other embedded memory systems will be very low.
Several techniques exist for providing redundancy in conventional memory design methodologies. In fact, such redundancy techniques have been largely responsible for the ever-increasing densities of the single-chip memories. Incorporating conventional redundancy schemes in embedded memory IP applications, however, has numerous deficiencies. First, such schemes provide a cost-effective solution only when the memory density is greater than a certain minimum number of bits. If the support circuitry needed for redundancy occupies more than 5% of the memory array area, the design is generally considered area-inefficient.
It should be apparent that such area requirements pose a significant difficulty in the field of embedded memory design. For example, the embedded memories are typically provided in various sizes (i.e., densities) and aspect ratios, and are distributed throughout the system (i.e, several memory instances may co-exist). The requirement of redundancy in smaller memory instances, accordingly, would result in an unacceptably large redundancy overhead (i.e., high area-inefficiency).
Further, conventional redundancy techniques typically involve placing fuse elements within the memory array for effectuating row or column redundancy. In general, they are placed in row decoders, storage areas for faulty addresses, column fuse banks, et cetera. Those skilled in the art should recognize that such schemes give rise to inefficient layouts because routing over fuse areas is not permitted, thereby causing routing congestion and related “place and route” problems. Also, because of the routing bottlenecks around the fuse areas, creating multi-level power grids may not be feasible in SOC circuits.
In addition, where laser-activated fuse technology is used, there are limits to how small such a fuse element needs to be. Accordingly, the size of fuse elements does not scale in correspondence with the size of memory core cells. Relatedly, the pitch of fuses normally does not match the pitch of memory cells. As a result, it would be very difficult to tile fuses and connect them appropriately in a dense periphery layout.
To address these and other redundancy-related issues, memory design techniques have been developed by the assignee of the present patent application wherein memory compilers are provided with the capability to configure fuse elements or other volatile storage elements outside the memory core that are capable of storing a repair signature. Such a repair signature can be used for hard repair (via fuse element data) or for soft repair (via volatile storage element data) of faulty locations. Although such techniques provide significant advantages, fuse compilers associated therewith for compiling an array of fuses with respect to one or more memory instances are beset with certain drawbacks. First, the fuse compiler system and user interface associated therewith are not easily adaptable to variable memory configurations. As is common in the semiconductor memory art, end users implementing a particular memory application by way of a compiler design may sometimes have to reconfigure the memory instances, including the redundancy requirements, in order to customize the application. When such modifications are made, the fuse count should also track the corresponding changes in the redundancy structures. Otherwise, an inaccurate fuse count will result, which renders the devices only partially functional at best or defective in general. Accordingly, the overall device yield will be negatively impacted. It should further be appreciated that because the performance requirements are stringent in all memory applications, even a single fuse missing in the required fuse count for a memory device will have significant consequences. In addition, more importantly, existing fuse compiler design techniques are not integrated with embedded memory test and repair methodologies in a satisfactory manner. Finally, some of these aforesaid concerns are also prevalent in situations where the repair signatures are stored in volatile registers for soft repair.